Oki Network Card MSM80C154S User Manual

ยก Semiconductor  
MSM80C154S/83C154S  
CMOS 8-bit Microcontroller  
GENERAL DESCRIPTION  
The MSM80C154S/MSM83C154S, designed for the high speed version of the existing  
MSM80C154/MSM83C154, is a higher performance 8-bit microcontroller providing low-power  
consumption.  
The MSM80C154S/MSM83C154S covers the functions and operating range of the existing  
MSM80C154/83C154/80C51F/80C31F.  
The MSM80C154S is identical to the MSM83C154S except it does not contain the internal  
program memory (ROM).  
FEATURES  
โ€ข Operating range  
Operating frequency  
: 0 to 3 MHz (V =2.2 to 6.0 V)  
cc  
0 to 12 MHz (V =3.0 to 6.0 V)  
cc  
0 to 24 MHz (V =4.5 to 6.0 V)  
cc  
Operating voltage  
Operating temperature  
: 2.2 to 6.0 V  
: โ€“40 to +85ยฐC (Operation at +125ยฐC conforms to  
the other specification.)  
โ€ข Fully static circuit  
โ€ข Upward compatible with the MSM80C51F/80C31F  
โ€ข On-chip program memory  
โ€ข On-chip data memory  
: 16K words x 8 bits ROM (MSM83C154S only)  
: 256 words x 8 bits RAM  
โ€ข External program memory address space : 64K bytes ROM (Max)  
โ€ข External data memory address space  
โ€ข I/O ports  
: 64K bytes RAM  
: 4 ports x 8 bits  
(Port 1, 2, 3, impedance programmable) : 32  
โ€ข 16-bit timer/counters  
: 3  
โ€ข Multifunctional serial port  
: I/O Expansion mode  
: UART mode (featuring error detection)  
โ€ข 6-source 2-priority level  
Interrupt and multi-level  
Interrupt available by programming IP and IE registers  
โ€ข Memory-mapped special function registers  
โ€ข Bit addressable data memory and SFRs  
โ€ข Minimum instruction cycle  
โ€ข Standby functions  
: 500 ns @ 24 MHz operation  
: Power-down mode (oscillator stop)  
Activated by software or hardware; providing  
ports with floating or active status  
The software power-down stet mode is termi-  
natedbyinterruptsignalenablingexecutionfrom  
the interrupted address.  
259  
 
P2.0  
P2.7  
P0.0  
P0.7  
DPH  
DPL  
CONTROL SIGNAL  
PLA  
R/W  
SIGNAL  
ROM  
SPECIAL  
FUNCTION  
REGISTER  
ADDRESS  
DECODER  
PCHL  
PCLL  
16K WORDS x 8BITS  
XTAL1  
XTAL2  
ALE  
PCH  
PCL  
IR  
AIR  
SP  
SENSE AMP  
C-ROM  
PSEN  
EA  
R/W AMP  
TR1  
T2CON  
TL2  
TH2  
ACC  
TR2  
RESET  
RAM  
256 WORDS  
x 8BITS  
RAMDP  
P1.0  
BR  
RCAP2L  
RCAP2H  
PSW  
TIMER/  
ALU  
COUNTER 2  
P1.7  
P3.0  
P3.7  
TH1  
TL1  
TH0  
TL0  
TMOD  
TCON  
IE  
INTERRUPT  
IP  
SBUF(T) SBUF(R)  
SERIAL IO  
SCON  
TIMER/COUNTER 0 & 1  
 
MSM80C154S/83C154S  
ยก Semiconductor  
PIN CONFIGURATION (TOP VIEW)  
P1.0/T2  
P1.1/T2EX  
P1.2  
1
2
3
4
5
6
7
8
9
40 VCC  
39 P0.0  
38 P0.1  
37 P0.2  
36 P0.3  
P1.3  
P1.4  
P1.5  
35 P0.4  
34 P0.5  
33 P0.6  
32 P0.7  
31 EA  
30 ALE  
29 PSEN  
28 P2.7  
27 P2.6  
26 P2.5  
25 P2.4  
24 P2.3  
23 P2.2  
22 P2.1  
21 P2.0  
P1.6  
P1.7  
RESET  
P3.0/RXD 10  
P3.1/TXD 11  
P3.2/INT0 12  
P3.3/INT1 13  
P3.4/T0 14  
P3.5/T1/HPDI 15  
P3.6/WR 16  
P3.7/RD 17  
XTAL2 18  
XTAL1 19  
VSS 20  
40-Pin Plastic DIP  
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ยก Semiconductor  
MSM80C154S/83C154S  
PIN CONFIGURATION (Continued)  
P1.5  
P1.6  
P0.4  
33  
1
2
P0.5  
32  
P1.7  
P0.6  
31  
3
RESET  
P0.7  
30  
4
P3.0/RXD  
NC  
EA  
29  
5
NC  
28  
6
P3.1/TXD  
P3.2/INT0  
P3.3/INT1  
P3.4/T0  
P3.5/T1/HPDI  
ALE  
27  
7
PSEN  
26  
8
P2.7  
25  
9
P2.6  
24  
10  
11  
P2.5  
23  
NC : No-connection pin  
44-Pin Plastic QFP  
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MSM80C154S/83C154S  
ยก Semiconductor  
P1.5  
P1.6  
P0.4  
1
2
33  
P0.5  
P0.6  
P0.7  
EA  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
P1.7  
3
RESET  
4
P3.0/RXD  
NC  
5
NC  
6
P3.1/TXD  
P3.2/INT0  
P3.3/INT1  
P3.4/T0  
P3.5/T1/HPDI  
ALE  
PSEN  
P2.7  
P2.6  
P2.5  
7
8
9
10  
11  
NC : No-connection pin  
44-Pin Plastic TQFP  
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ยก Semiconductor  
MSM80C154S/83C154S  
PIN CONFIGURATION (Continued)  
P0.3 40  
P0.2 41  
P0.1 42  
P0.0 43  
VCC 44  
28 P2.4  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
P2.3  
P2.2  
P2.1  
P2.0  
NC  
P1.0/T2  
P1.1/T2EX  
P1.2  
1
2
3
4
5
6
NC  
VSS  
XTAL1  
XTAL2  
P3.7/RD  
P3.6/WR  
P1.3  
P1.4  
NC : No-connection pin  
44-Pin Plastic QFJ  
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MSM80C154S/83C154S  
ยก Semiconductor  
PIN DESCRIPTIONS  
Symbol  
Descriptipn  
P0.0 to P0.7 Bidirectional I/O ports. They are also the data/address bus (input/output of data and output of  
lower 8-bit address when external memory is accessed).  
They are open-drain outputs when used as I/O ports, but 3-state outputs when used as data/address  
bus.  
P1.0 to P1.7 P1.0 to P1.7 are quasi-bidirectional I/O ports. They are pulled up internally when used as input  
ports. Two of them have the following secondary functions:  
โ€ขP1.0 (T2)  
โ€ขP1.1 (T2EX)  
: used as external clock input pins for the timer/counter 2.  
: used as trigger input for the timer/counter 2 to be reloaded or captured;  
causing the timer/counter 2 interrupt.  
P2.0 to P2.7 P2.0 to P2.7 are quasi-bidirectional I/O ports. They also output the higher 8-bit address when  
an external memory is accessed. They are pulled up internally when used as input ports.  
P3.0 to P3.7 P3.0 to P3.7 are quasi-bidirectional I/O ports. They are pulled up internally when used as input  
ports. They also have the following secondary functions:  
โ€ขP3.0 (RXD)  
Serial data input/output in the I/O expansion mode and serial data input in the UART mode when  
the serial port is used.  
โ€ข3.1 (TXD)  
Synchronous clock output in the I/O expansion mode and serial data output in the UART mode  
when the serial port is used.  
โ€ข3.2 (INT0)  
Used as input pin for the external interrupt 0, and as count-up control pin for the timer/counter 0.  
โ€ข3.3 (INT1)  
Used as input pin for the external interrupt 1, and as count-up control pin for the timer/counter 1.  
โ€ข3.4 (T0)  
Used as external clock input pin for the timer/counter 0.  
โ€ข3.5 (T1)  
Used as external clock input pin for the timer/counter 1 and power-down-mode control input pin.  
โ€ข3.6 (WR)  
Output of the write-strobe signal when data is written into external data memory.  
โ€ข3.7 (RD)  
Output of the read-strobe signal when data is read from external data memory.  
ALE  
PSEN  
EA  
Address latch enable output for latching the lower 8-bit address during external memory access.  
Two ALE pulses are activated per machine cycle except during external data memory access at  
which time one ALE pulse is skipped.  
Program store enable output which enables the external memory output to the bus during external  
program memory access. Two PSEN pulses are activated per machine cycle except during  
external data memory access at which two PSEN pulses are skipped.  
When EA is held at "H" level, the MSM 83C154S executes instructions from internal program  
memory at address 0000H to 3FFFH, and executes instructions from external program memory  
above address 3FFFH.  
When EA is held at "L" level, the MSM80C154S/MSM83C154S executes instructions from external  
program memory for all addresses.  
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MSM80C154S/83C154S  
PIN Descriptions (Continued)  
Symbol  
Descriptipn  
RESET  
If this pin remains "H" for at least one machine cycle, the MSM80C154S/MSM83C154S is reset.  
Since this pin is pulled down internally, a power-on reset is achieved by simply connecting a  
capacitor between VCC and this pin.  
XTAL1  
XTAL2  
VCC  
Oscillator inverter input pin. External clock is input through XTAL1 pin.  
Oscillator inverter output pin.  
Power supply pin during both normal operation and standby operations.  
GND pin.  
VSS  
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MSM80C154S/83C154S  
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REGISTERS  
Diagram of Special Function Registers  
BIT ADDRESS  
DIRECT  
REGISTER  
NAME  
ADDRESS  
b7  
FF  
b6  
FE  
F6  
E6  
D6  
b5  
FD  
F5  
E5  
D5  
b4  
FC  
F4  
E4  
D4  
b3  
FB  
F3  
E3  
D3  
b2  
FA  
F2  
E2  
D2  
b1  
F9  
F1  
E1  
D1  
b0  
F8  
F0  
E0  
D0  
IOCON  
B
0F8H (248)  
0F0H (240)  
0E0H (224)  
0D0H (208)  
0CDH (205)  
0CCH (204)  
0CBH (203)  
0CAH (202)  
0C8H (200)  
0B8H (184)  
0B0H (176)  
0A8H (168)  
0A0H (160)  
99H (153)  
98H (152)  
90H (144)  
8DH (141)  
8CH (140)  
8BH (139)  
8AH (138)  
89H (137)  
88H (136)  
87H (135)  
83H (131)  
82H (130)  
81H (129)  
80H (128)  
F7  
E7  
D7  
ACC  
PSW  
TH2  
TL2  
RCAP2H  
RCAP2L  
T2CON  
IP  
CF  
BF  
B7  
AF  
A7  
CE  
BE  
B6  
AE  
A6  
CD  
BD  
B5  
AD  
A5  
CC  
BC  
B4  
AC  
A4  
CB  
BB  
B3  
AB  
A3  
CA  
BA  
B2  
AA  
A2  
C9  
B9  
B1  
A9  
A1  
C8  
B8  
B0  
A8  
A0  
P3  
IE  
P2  
SBUF  
SCON  
P1  
9F  
97  
9E  
96  
9D  
95  
9C  
94  
9B  
93  
9A  
92  
99  
91  
98  
90  
TH1  
TH0  
TL1  
TL0  
TMOD  
TCON  
PCON  
DPH  
DPL  
SP  
8F  
87  
8E  
86  
8D  
85  
8C  
84  
8B  
83  
8A  
82  
89  
81  
88  
80  
P0  
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MSM80C154S/83C154S  
Special Function Registers  
Timer mode register (TMOD)  
MSB  
7
LSB  
NAME  
ADDRESS  
6
5
4
3
2
1
0
TMOD  
BIT LOCATION  
TMOD.0  
89H  
FLAG  
M0  
GATE  
C/T  
M1  
M0  
GATE  
C/T  
M1  
M0  
FUNCTION  
Timer/counter 0 mode setting  
M1  
0
M0  
0
8-bit timer/counter with 5-bit prescalar.  
16-bit timer/counter.  
0
1
1
0
8-bit timer/counter with 8-bit auto reloading.  
TMOD.1  
TMOD.2  
M1  
1
1
Timer/counter 0 separated into TLO (8-bit) timer/counter  
and TH0 (8-bit) timer/counter. TF0 is set by TL0 carry, and  
TF1 is set by TH0 carry.  
C/T  
Timer/counter 0 count clock designation control bit.  
XTAL1โ€ข2 divided by 12 clocks is the input applied to timer/counter 0 when  
C/T = "0".  
The external clock applied to the T0 pin is the input applied to timer/counter 0  
when C/T = "1".  
TMOD.3  
TMOD.4  
GATE  
M0  
When this bit is "0", the TR0 bit of TCON (timer control register) is used to  
control the start and stop of timer/counter 0 counting.  
If this bit is "1", timer/counter 0 starts counting when both the TR0 bit of TCON  
and INT0 pin input signal are "1", and stops counting when either is changed  
to "0".  
M1  
0
M0  
0
Timer/counter 1 mode setting  
8-bit timer/counter with 5-bit prescalar.  
16-bit timer/counter  
0
1
1
0
8-bit timer/counter with 8-bit auto reloading.  
Timer/counter 1 operation stopped.  
TMOD.5  
TMOD.6  
M1  
1
1
C/T  
Timer/counter 1 count clock designation control bit.  
XTAL1โ€ข2 divided by 12 clocks is the input applied to timer/counter 1 when  
C/T = "0".  
The external clock applied to the T1 pin is the input applied to timer/counter 1  
when C/T = "1".  
TMOD.7  
GATE  
When this bit is "0", the TR1 bit of TCON is used to control the start and stop of  
timer/counter 1 counting.  
If this bit is "1", timer/counter 1 starts counting when both the TR1 bit of TCON  
and INT1 pin input signal are "1", and stops counting when either is changed  
to "0".  
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MSM80C154S/83C154S  
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Power control register (PCON)  
MSB  
7
LSB  
NAME  
ADDRESS  
6
5
4
3
2
1
0
PCON  
BIT LOCATION  
PCON.0  
87H  
FLAG  
IDL  
SMOD  
HPD  
RPD  
โ€”
GF1  
GF0  
PD  
IDL  
FUNCTION  
IDLE mode is set when this bit is set to "1". CPU operations are stopped when  
IDLE mode is set, but XTAL1โ€ข2, timer/counters 0, 1 and 2, the interrupt circuits,  
and the serial port remain active. IDLE mode is cancelled when the CPU is reset  
or when an interrupt is generated.  
PCON.1  
PD  
PD mode is set when this bit is set to "1". CPU operations and XTAL1โ€ข2 are  
stopped when PD mode is set. PD mode is cancelled when the CPU is reset or  
when an interrupt is generated.  
PCON.2  
PCON.3  
PCON.4  
PCON.5  
GF0  
GF1  
โ€”
General purpose bit.  
General purpose bit.  
Reserved bit. The output data is "1", if the bit is read.  
RPD  
This bit is used to specify cancellation of CPU power down mode (IDLE or PD) by an  
interrupt signal.  
Power-down mode cannot be cancelled by an interrupt signal if the interrupt is not  
enabled by IE (interrupt enable register) when this bit is "0".  
If the interrupt flag is set to "1" by an interrupt request signal when this bit is  
"1" (even if interrupt is disabled), the program is executed from the next address  
of the power-down-mode setting instruction.  
The flag is reset to "0" by software.  
PCON.6  
PCON.7  
HPD  
The hard power-down setting mode in enabled when this bit is set to "1".  
If the level of the power failure detect signal applied to the HPDI pin (pin 3.5)  
is changed from "1" to "0" when this bit is "1", XTAL1โ€ข2 oscillation is stopped and  
the system is put into hard power down mode. HPD mode is cancelled when the  
CPU is reset.  
SMOD  
When the timer/counter 1 carry signal is used as a clock in mode 1, 2 or 3 of  
the serial port, this bit has the following functions.  
The serial port operation clock is reduced by 1/2 when the bit is "0" for delayed  
processing. When the bit is "1", the serial port operation clock is normal  
for faster processing.  
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MSM80C154S/83C154S  
Timer control register (TCON)  
MSB  
7
LSB  
NAME  
ADDRESS  
6
5
4
3
2
1
0
TCON  
BIT LOCATION  
TCON.0  
88H  
FLAG  
IT0  
TF1  
TR1  
TF0  
TR0  
IE1  
IT1  
IE0  
IT0  
FUNCTION  
External interrupt 0 signal is used in level-detect mode when this bit is "0" and in  
trigger detect mode when "1".  
TCON.1  
IE0  
Interrupt request flag for external interrupt 0.  
The bit is reset automatically when an interrupt is serviced.  
The bit can be set and reset by software when IT0 = "1".  
TCON.2  
TCON.3  
IT1  
IE1  
External interrupt 1 signal is used in level detect mode when this bit is "0", and in  
trigger detect mode when "1".  
Interrupt request flag for external interrupt 1.  
The bit is reset automatically when an interrupt is serviced.  
The bit can be set and reset by software when IT1 = "1".  
TCON.4  
TCON.5  
TR0  
TF0  
Counting start and stop control bit for timer/counter 0.  
Timer/counter 0 starts counting when this bit is "1", and stops counitng when "0".  
Interrupt request flag for timer interrupt 0.  
The bit is reset automatically when an interrupt is serviced.  
The bit is set to "1" when a carry signal is generated from timer/counter 0.  
TCON.6  
TCON.7  
TR1  
TF1  
Counting start and stop control bit for timer/counter 1.  
The timer/counter 1 starts counting when this bit is "1", and stops counting when "0".  
Interrupt request flag for timer interrupt 1.  
The bit is reset automatically when interrupt is serviced.  
The bit is set to "1" when carry signal is generated from timer/counter 1.  
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MSM80C154S/83C154S  
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Serial port control register (SCON)  
MSB  
LSB  
NAME  
ADDRESS  
7
6
5
4
3
2
1
0
SCON  
BIT LOCATION  
SCON.0  
98H  
FLAG  
RI  
SM0  
SM1  
SM2  
REN  
TB8  
RB8  
TI  
RI  
FUNCTION  
"End of serial port reception" interrupt request flag.  
This flag must be reset by software during interrupt service routine.  
This flag is set after the eighth bit of data has been received when in mode 0, or  
by the STOP bit when in any other mode.  
In mode 2 or 3, however, RI is not set if the RB8 data is "0" with SM2 = "1".  
RI is set in mode 1 if STOP bit is received when SM2 = "1".  
SCON.1  
SCON.2  
TI  
"End of serial port tramsmission" interrupt request flag. This flag must be reset  
by software during interrupt service routine.  
This flag is set after the eighth bit of data has been sent when in mode 0, or after  
the last bit of data has been sent when in any other mode.  
RB8  
The ninth bit of data received in mode 2 or 3 is passed to RB8.  
The STOP bit is applied to RB8 if SM2 = "0" when in mode 1.  
RB8 can not be used in mode 0.  
SCON.3  
SCON.4  
TB8  
The TB8 data is sent as the ninth data bit when in mode 2 or 3.  
Any desired data can be set in TB8 by software.  
REN  
Reception enable control bit.  
No reception when REN = "0".  
Reception enabled when REN = "1".  
SCON.5  
SM2  
If the ninth bit of received data is "0" with SM2 = "1" in mode 2 or 3, the "end of  
reception" signal is not set in the RI flag.  
The "end of reception" signal set in the RI flag if the STOP bit is not "1" when  
SM2 = "1" in mode 1.  
SCON.6  
SCON.7  
SM1  
SM0  
SM0  
SM1  
MODE  
0
0
1
1
0
1
0
1
0
1
2
3
8-bit shift register I/O  
8-bit UART variable baud rate  
9-bit UART 1/32 XTAL1, 1/64 XTAL1 baud rate  
9-bit UART variable baud rate  
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MSM80C154S/83C154S  
Interrupt enable register (IE)  
MSB  
7
LSB  
NAME  
ADDRESS  
6
5
4
3
2
1
0
IE  
BIT LOCATION  
IE.0  
0A8H  
FLAG  
EX0  
EA  
โ€”
ET2  
ES  
ET1  
EX1  
ET0  
EX0  
FUNCTION  
Interrupt control bit for external interrupt 0.  
Interrupt disabled when bit is "0".  
Interrupt enabled when bit is "1".  
IE.1  
IE.2  
IE.3  
IE.4  
IE.5  
ET0  
EX1  
ET1  
ES  
Interrupt control bit for timer interrupt 0.  
Interrupt disabled when bit is "0".  
Interrupt enabled when bit is "1".  
Interrupt control bit for external interrupt 1.  
Interrupt disabled when bit is "0".  
Interrupt enabled when bit is "1".  
Interrupt control bit for timer interrupt 1.  
Interrupt disabled when bit is "0".  
Interrupt enabled when bit is "1".  
Interrupt control bit for serial port.  
Interrupt disabled when bit is "0".  
Interrupt enabled when bit is "1".  
ET2  
Interrupt control bit for timer interrupt 2.  
Interrupt disabled when bit is "0".  
Interrupt enabled when bit is "1".  
IE.6  
IE.7  
โ€”
EA  
Reserved bit. The output data is "1" if the bit is read.  
Overall interrupt control bit.  
All interrupts are disabled when bit is "0".  
All interrupts are controlled by IE.0 thru IE.5 when bit is "1".  
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Interrupt priority register (IP)  
MSB  
7
LSB  
NAME  
ADDRESS  
6
5
4
3
2
1
0
IP  
BIT LOCATION  
IP.0  
0B8H  
FLAG  
PX0  
PCT  
โ€”
PT2  
PS  
PT1  
PX1  
PT0  
PX0  
FUNCTION  
Interrupt priority bit for external interrupt 0.  
Priority is assigned when bit is "1".  
IP.1  
IP.2  
IP.3  
IP.4  
IP.5  
PT0  
PX1  
PT1  
PS  
Interrupt priority bit for timer interrupt 0.  
Priority is assigned when bit is "1".  
Interrupt priority bit for external interrupt 1.  
Priority is assigned when bit is "1".  
Interrupt priority bit for timer interrupt 1.  
Priority is assigned when bit is "1".  
Interrupt priority bit for serial port.  
Priority is assigned when bit is "1".  
PT2  
Interrupt priority bit for timer interrupt 2.  
Priority is assigned when bit is "1".  
IP.6  
IP.7  
โ€”
Reserved bit. The output data is "1" if the bit is read.  
Priority interrupt circuit control bit.  
PCT  
The priority register contents are valid and priority assigned interrupts can be  
processed when this bit is "0". When the bit is "1", the priority interrupt circuit is  
stopped, and interrupts can only be controlled by the interrupt enable register (IE).  
274  
 
ยก Semiconductor  
MSM80C154S/83C154S  
Program status word register (PSW)  
MSB  
LSB  
NAME  
ADDRESS  
7
6
5
4
3
2
1
0
PSW  
BIT LOCATION  
PSW.0  
0D0H  
FLAG  
P
CY  
AC  
F0  
RS1  
RS0  
OV  
F1  
P
FUNCTION  
Accumulator (ACC) parity indicator.  
This bit is "1" when the "1" bit number in the accumulator is an odd number, and  
"0" when an even number.  
PSW.1  
PSW.2  
F1  
User flag which may be set to "0" or "1" as desired by the user.  
OV  
Overflow flag which is set if the carry C6 from bit 6 of the ALU or CY is "1" as a  
result of an arithmetic operation. The flag is also set to "1" if the resultant product  
of executing multiplication instruction (MUL AB) is greater than 0FFH, but is reset  
to "0" if the product is less than or equal to 0FFH.  
PSW.3  
PSW.4  
RS0  
RS1  
RAM register bank switch  
RS1  
0
RS0  
0
BANK  
RAM ADDRESS  
0
1
2
3
00H - 07H  
08H - 0FH  
10H - 17H  
18H - 1FH  
0
1
1
0
1
1
PSW.5  
PSW.6  
F0  
User flag which may be set to "0" or "1" as desired by the user.  
AC  
Auxiliary carry flag.  
This flag is set to "1" if a carry C3 is generated from bit 3 of the ALU as a result of  
executing an arithmetic operation instruction.  
In all other cases, the flag is reset to "0".  
PSW.7  
CY  
Main carry flag.  
This flag is set to "1" if a carry C7 is generated from bit 7 of the ALU as result of  
executing an arithmetic operation instruction.  
If a carry C7 is not generated, the flag is reset to "0".  
275  
 
MSM80C154S/83C154S  
ยก Semiconductor  
I/O control register (IOCON)  
MSB  
7
LSB  
NAME  
ADDRESS  
6
5
4
3
2
1
0
IOCON  
BIT LOCATION  
IOCON.0  
0F8H  
FLAG  
ALF  
โ€”
T32  
SERR  
IZC  
P3HZ  
P2HZ  
P1HZ  
ALF  
FUNCTION  
If CPU power down mode (PD, HPD) is activated with this bit set to "1", the  
outputs from ports 0, 1, 2, and 3 are switched to floating status.  
When this bit is "0", ports 0, 1, 2, and 3 are in output mode.  
IOCON.1  
IOCON.2  
IOCON.3  
IOCON.4  
P1HZ  
P2HZ  
P3HZ  
IZC  
Port 1 becomes a high impedance input port when this bit is "1".  
Port 2 becomes a high impedance input port when this bit is "1".  
Port 3 becomes a high impedance input port when this bit is "1".  
The 10 kW pull-up resistor for ports 1, 2, and 3 is switched off when this bit  
is "1", leaving only the 100 kW pull-up resistor.  
IOCON.5  
SERR  
Serial port reception error flag.  
This flag is set to "1" if an overrun or framing error is generated when data is  
received at a serial port.  
The flag is reset by software.  
IOCON.6  
IOCON.7  
T32  
โ€”
Timer/counters 0 and 1 are connected serially to from a 32-bit timer/counter  
when this bit is set to "1".  
TF1 of TCON is set if a carry is generated in the 32-bit timer/counter.  
Leave this bit at "0".  
276  
 
ยก Semiconductor  
MSM80C154S/83C154S  
Timer 2 control register (T2CON)  
MSB  
LSB  
NAME  
ADDRESS  
7
6
5
4
3
2
1
0
T2CON  
BIT LOCATION  
T2CON.0  
0C8H  
FLAG  
CP/RL2  
TF2  
EXF2  
RCLK  
TCLK  
EXEN2  
TR2  
C/T2  
CP/RL2  
FUNCTION  
Capture mode is set when TCLK + RCLK = "0" and CP/RL2 = "1".  
16-bit auto reload mode is set when TCLK + RCLK = "0" and CP/RL2 = "0".  
CP/RL2 is ignored when TCLK + RCLK = "1".  
T2CON.1  
T2CON.2  
C/T2  
Timer/counter 2 count clock designation control bit.  
The internal clocks (XTAL1โ€ข2 รท 12, XTAL1โ€ข2 รท 2) are used when this bit is "0",  
and the external clock applied to the T2 pin is passed to timer/counter 2 when  
the bit is "1".  
TR2  
Timer/counter 2 counting start and stop control bit.  
Timer/counter 2 commences counting when this bit is "1" and stops counting  
when "0".  
T2CON.3  
T2CON.4  
EXEN2  
TCLK  
T2EX timer/counter 2 external control signal control bit.  
Input of the T2EX signal is disabled when this bit is "0", and enabled when "1".  
Serial port transmit circuit drive clock control bit.  
Timer/counter 2 is switched to baud rate generator mode when this bit is "1",  
and the timer/counter 2 carry signal becomes the serial port transmit clock.  
Note, however, that the serial ports can only use the timer/counter 2 carry signal  
in serial port modes 1 and 3.  
T2CON.5  
T2CON.6  
T2CON.7  
RCLK  
EXF2  
TF2  
Serial port receive circuit drive clock control bit.  
Timer/counter 2 is switched to baud rate generator mode when this bit is "1",  
and the timer/counter 2 carry signal becomes the serial port transmit clock.  
Note, however, that the serial ports can only use the timer/counter 2 carry signal  
in serial port modes 1 and 3.  
Timer/counter 2 external flag.  
This bit is set to "1" when the T2EX timer/counter 2 external control signal level  
is changed from "1" to "0" while EXEN2 = "1".  
This flag serves as the timer interrupt 2 request signal. If an interrupt is  
generated, EXF2 must be reset to "0" by software.  
Timer/counter 2 carry flag.  
This bit is set to "1" by a carry signal when timer/counter 2 is in 16-bit auto  
reload mode or in capture mode.  
This flag serves as the timer interrupt 2 request signal. If an interrupt is  
generated, TF2 must be reset to "0" by software.  
277  
 
MSM80C154S/83C154S  
ยก Semiconductor  
MEMORY MAPS  
Program Area  
65535 0FFFFH  
Timer interrupt 2 start  
S I/O interrupt start  
43  
35  
27  
19  
002BH  
0023H  
001BH  
0013H  
Timer interrupt 1 start  
External interrupt 1 start  
16384 4000H  
16383 3FFFH  
Timer interrupt 0 start  
11  
000BH  
44 002CH  
43 002BH  
External interrupt 0 start  
3
2
1
0
0003H  
0002H  
0001H  
0000H  
0
7
6
5
4
3
2 1  
0
CPU reset start  
278  
 
ยก Semiconductor  
MSM80C154S/83C154S  
Internal Data Memory and Special Function Register Layout Diagram  
HEX  
0FF  
IOCON  
B
ACC  
PSW  
TH2  
FFH~F8H  
F7H~F0H  
E7H~E0H  
D7H~D0H  
248(0F8H)  
240(0F0H)  
224(0E0H)  
208(0D0H)  
205(0CDH)  
204(0CCH)  
203(OCBH)  
202(0CAH)  
200(0C8H)  
184(0B8H)  
176(0B0H)  
168(0A8H)  
160(0A0H)  
153( 99H)  
152( 98H)  
144( 90H)  
141( 8DH)  
140( 8CH)  
139( 8BH)  
138( 8AH)  
137( 89H)  
136( 88H)  
135( 87H)  
131( 83H)  
130( 82H)  
129( 81H)  
128( 80H)  
TL2  
RCAP2H  
RCAP2L  
T2CON  
IP  
CFH~C8H  
BFH~B8H  
B7H~B0H  
AFH~A8H  
A7H~A0H  
P3  
IE  
P2  
USER DATA RAM  
SBUF  
SCON  
P1  
TH1  
TH0  
9FH~98H  
97H~90H  
TL1  
TL0  
TMOD  
TCON  
PCON  
DPH  
DPL  
SP  
8FH~88H  
87H~80H  
P0  
80  
7F  
USER DATA RAM  
BIT RAM  
30  
2F 7F  
78  
0
20  
7
BIT ADDRESSING  
1F R7  
BANK3  
BANK2  
BANK1  
BANK0  
18 R0  
17 R7  
10 R0  
0F R7  
08 R0  
07 R7  
DATA ADDRESSING  
00 R0  
279  
 
MSM80C154S/83C154S  
ยก Semiconductor  
Diagram of Internal Data Memory (RAM)  
0FFH  
255  
128  
USER DATA RAM  
80H  
7FH  
127  
48  
USER DATA RAM  
30H  
2FH  
2EH  
2DH  
2CH  
2BH  
2AH  
29H  
28H  
27H  
26H  
25H  
24H  
23H  
22H  
21H  
7F  
77  
6F  
67  
5F  
57  
4F  
47  
3F  
37  
2F  
27  
1F  
17  
0F  
07  
7E  
76  
6E  
66  
5E  
56  
4E  
46  
3E  
36  
2E  
26  
1E  
16  
0E  
06  
7D  
75  
6D  
65  
5D  
55  
4D  
45  
3D  
35  
2D  
25  
1D  
15  
0D  
05  
7C  
74  
6C  
64  
5C  
54  
4C  
44  
3C  
34  
2C  
24  
1C  
14  
0C  
04  
7B  
73  
6B  
63  
5B  
53  
4B  
43  
3B  
33  
2B  
23  
1B  
13  
0B  
03  
7A  
72  
6A  
62  
5A  
52  
4A  
42  
3A  
32  
2A  
22  
1A  
12  
0A  
02  
79  
71  
69  
61  
59  
51  
49  
41  
39  
31  
29  
21  
19  
11  
09  
01  
78  
70  
68  
60  
58  
50  
48  
40  
38  
30  
28  
20  
18  
10  
08  
00  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
20H  
1FH  
32  
31  
Bank 3  
18H  
17H  
24  
23  
Bank 2  
Bank 1  
Bank 0  
10H  
0FH  
16  
15  
08H  
07H  
8
7
00H  
0
280  
 
ยก Semiconductor  
MSM80C154S/83C154S  
ABSOLUTE MAXIMUM RATINGS  
Parameter  
Supply voltage  
Symbol  
VCC  
Condition  
Ta=25ยฐC  
Ta=25ยฐC  
โ€”
Rating  
โ€“0.5 to 7  
Unit  
V
Input voltage  
VI  
โ€“0.5 to VCC+0.5  
โ€“55 to +150  
V
Storage temperature  
TSTG  
ยฐC  
RECOMMENDED OPERATING CONDITIONS  
Parameter  
Power supply voltage  
Memory retension voltage  
Oxcillation frequency  
Symbol  
VCC  
Condition  
See below  
Range  
2.0 to 6.0  
2.0 to 6.0  
1 to 24  
Unit  
V
VCC  
fOSC=0 Hz (Oscillation stop)  
See below  
V
fOSC  
MHz  
MHz  
External clock operating  
frequency  
fEXTCLK  
See below  
0 to 24  
Ambient temperature  
Ta  
โ€”
โ€“40 to +85  
ยฐC  
*1 Depends on the specifications for the oscillator or ceramic resonater.  
12  
1
5
4
3
3
2
6
1
12  
0.6  
0.5  
20  
24  
2.2  
2
3
4
5
6
Power Supply Voltage (VCC  
)
281  
 
MSM80C154S/83C154S  
ยก Semiconductor  
ELECTRICAL CHARACTERISTICS  
DC Characteristics 1  
(VCC=4.0 to 6.0 V, VSS=0 V, Ta=-40 to +85ยฐC)  
Meas-  
uring  
Parameter  
Input Low Voltage  
Symbol  
VIL  
Condition  
Min.  
โ€“0.5  
Typ.  
โ€”
Max.  
Unit  
circuit  
โ€”
V
V
V
V
0.2 VCCโ€“0.1  
Except XTAL1, EA,  
and RESET  
Input High Voltage  
VIH  
0.2 VCC+0.9  
0.7 VCC  
โ€”
โ€”
V
V
CC+0.5  
CC+0.5  
0.45  
Input High Voltage  
Output Low Voltage  
(PORT 1, 2, 3)  
VIH1  
XTAL1, RESET and EA  
โ€”
VOL  
IOL=1.6 mA  
โ€”
Output Low Voltage  
(PORT 0, ALE, PSEN)  
VOL1  
IOL=3.2 mA  
โ€”
โ€”
โ€”
V
V
0.45  
โ€”
1
IOH=โ€“60 mA  
2.4  
Output High Voltage  
(PORT 1, 2, 3)  
VCC=5 Vยฑ10%  
VOH  
IOH=โ€“30 mA  
IOH=โ€“10 mA  
IOH=โ€“400 mA  
0.75 VCC  
0.9 VCC  
โ€”
โ€”
V
V
โ€”
โ€”
2.4  
โ€”
V
โ€”
Output High Voltage  
V
CC=5 Vยฑ10%  
IOH=โ€“150 mA  
IOH=โ€“40 mA  
VI=0.45 V  
VOH1  
(PORT 0, ALE, PSEN)  
0.75 VCC  
0.9 VCC  
โ€”
โ€”
V
V
โ€”
โ€”
Logical 0 Input Current/  
Logical 1 Output Current/  
(PORT 1, 2, 3)  
Logical 1 to 0 Transition  
Output Current (PORT 1, 2, 3)  
Input Leakage Current  
IIL / IOH  
ITL  
โ€“5  
โ€”
โ€“20  
mA  
โ€“80  
VO=0.45 V  
2
VI=2.0 V  
โ€“190  
mA  
โ€“500  
ILI  
RRST  
CIO  
VSS < VI < VCC  
โ€”
20  
โ€”
โ€”
โ€”
40  
โ€”
1
mA  
kW  
pF  
3
2
ยฑ10  
125  
10  
(PORT 0 floating, EA)  
RESET Pull-down Resistance  
โ€”
Ta=25ยฐC, f=1 MHz  
(except XTAL1)  
โ€”
Pin Capacitance  
โ€”
4
Power Down Current  
IPD  
mA  
50  
282  
 
ยก Semiconductor  
MSM80C154S/83C154S  
Maximum power supply current normal operation I (mA)  
CC  
VCC  
Freq  
4 V  
5 V  
6 V  
1 MHz  
3 MHz  
12 MHz  
16 MHz  
20 MHz  
2.2  
3.9  
3.1  
5.2  
4.1  
7.0  
12.0  
16.0  
19.0  
16.0  
20.0  
25.0  
20.0  
25.0  
30.0  
VCC  
Freq  
4.5 V  
5 V  
6 V  
24 MHz  
25.0  
29.0  
35.0  
Maximum power supply current idle mode I (mA)  
CC  
VCC  
Freq  
4 V  
5 V  
6 V  
1 MHz  
3 MHz  
12 MHz  
16 MHz  
20 MHz  
0.8  
1.2  
3.1  
3.8  
4.5  
1.2  
1.7  
4.4  
5.5  
6.4  
1.6  
2.3  
5.9  
7.3  
8.6  
VCC  
Freq  
4.5 V  
5 V  
6 V  
24 MHz  
6.4  
7.4  
9.8  
283  
 
MSM80C154S/83C154S  
DC Characteristics 2  
ยก Semiconductor  
(VCC=2.2 to 4.0 V, VSS=0 V, Ta=-40 to +85ยฐC)  
Meas-  
uring  
Parameter  
Input Low Voltage  
Input High Voltage  
Symbol  
VIL  
Condition  
Min.  
โ€“0.5  
Typ.  
โ€”
Max.  
Unit  
circuit  
โ€”
V
V
V
V
0.25 VCCโ€“0.1  
Except XTAL1, EA,  
and RESET  
VIH  
0.25 VCC+0.9  
โ€”
V
V
CC+0.5  
CC+0.5  
0.1  
Input High Voltage  
Output Low Voltage  
(PORT 1, 2, 3)  
VIH1  
XTAL1, RESET, and EA 0.6 VCC+0.6  
โ€”
VOL  
IOL=10 mA  
IOL=20 mA  
IOH=โ€“5 mA  
IOH=โ€“20 mA  
โ€”
โ€”
โ€”
Output Low Voltage  
(PORT 0, ALE, PSEN)  
VOL1  
VOH  
โ€”
โ€”
V
V
0.1  
โ€”
1
2
Output High Voltage  
Output High Voltage  
0.75 VCC  
0.75 VCC  
โ€“5  
(PORT 1, 2, 3)  
(PORT 0, ALE, PSEN)  
VOH1  
IIL / IOH  
ITL  
โ€”
V
โ€”
Logical 0 Input Current/  
Logical 1 Output Current/  
(PORT 1, 2, 3)  
Logical 1 to 0 Transition  
Output Current (PORT 1, 2, 3)  
Input Leakage Current  
VI=0.1 V  
VO=0.1 V  
โ€“10  
โ€“80  
mA  
mA  
โ€“40  
โ€“300  
VI=1.9 V  
โ€”
ILI  
RRST  
CIO  
VSS < VI < VCC  
โ€”
20  
โ€”
โ€”
โ€”
40  
โ€”
1
mA  
kW  
pF  
3
2
ยฑ10  
125  
10  
(PORT 0 floating, EA)  
RESET Pull-down Resistance  
โ€”
Ta=25ยฐC, f=1 MHz  
(except XTAL1)  
โ€”
Pin Capacitance  
โ€”
4
Power Down Current  
IPD  
mA  
10  
284  
 
ยก Semiconductor  
MSM80C154S/83C154S  
Maximum power supply current normal operation I (mA)  
CC  
VCC  
Freq  
2.2 V  
3.0 V  
4.0 V  
1 MHz  
3 MHz  
12 MHz  
16 MHz  
0.9  
1.8  
โ€”
1.4  
2.4  
8.0  
โ€”
2.2  
4.3  
12.0  
16.0  
โ€”
Maximum power supply current idle mode I (mA)  
CC  
VCC  
Freq  
2.2 V  
3.0 V  
4.0 V  
1 MHz  
3 MHz  
12 MHz  
16 MHz  
0.3  
0.5  
โ€”
0.5  
0.8  
2.0  
โ€”
0.8  
1.2  
3.1  
3.8  
โ€”
285  
 
MSM80C154S/83C154S  
Measuring circuits  
ยก Semiconductor  
1
2
VCC  
VSS  
3
(*2)  
V
(*1)  
VCC  
VSS  
4
VIH  
VIL  
IO  
A
V
A
A
VCC  
(*2)  
V
VCC  
VIH  
VIL  
VIH  
VIL  
A
VSS  
VSS  
*1: Repeated for specified input pins.  
*2: Repeated for specified output pins.  
*3: Input logic for specified status.  
286  
 
ยก Semiconductor  
MSM80C154S/83C154S  
AC Characteristics  
(1) External program memory access AC characteristics  
VCC=2.2 to 6.0V, VSS=0V, Ta=โ€“40ยฐC to +85ยฐC  
PORT 0, ALE, and PSEN connected with 100pF load, other connected with 80pF load  
*1  
Variable clock from  
Parameter  
Symble  
Unit  
1 to 24 MHz  
Min.  
41.7  
Max.  
1000  
โ€”
XTAL1, XTAL 2 Oscillation Cycle  
ALE Signal Width  
tCLCL  
tLHLL  
ns  
ns  
2tCLCL-40  
Address Setup Time  
tAVLL  
tLLAX  
tLLPL  
1tCLCL-15  
1tCLCL-35  
โ€”
โ€”
โ€”
ns  
ns  
ns  
(to ALE Falling Edge)  
Address Hold Time  
(from ALE Falling Edge)  
Instruction Data Read Time  
(from ALE Falling Edge)  
From ALE Falling Edge to PSEN  
Falling Edge  
4tCLCL-100  
tLLPL  
tPLPH  
tPLIV  
1tCLCL-30  
3tCLCL-35  
โ€”
โ€”
โ€”
ns  
ns  
ns  
PSEN Signal Width  
Instruction Data Read Time  
(from PSEN Falling Edge)  
Instruction Data Hold Time  
(from PSEN Rising Edge)  
Bus Floating Time after Instruction  
Data Read (from PSEN Rising Edge)  
Instruction Data Read Time  
(from Address Output)  
Bus Floating Time(PSEN Rising  
Edge from Address float)  
Address Output Time from PSEN  
Rising Edge  
3tCLCL-45  
tPXIX  
tPXIZ  
tAVIV  
tAZPL  
tPXAV  
0
โ€”
1tCLCL-20  
5tCLCL-105  
โ€”
ns  
ns  
ns  
ns  
ns  
โ€”
โ€”
0
1tCLCL-20  
โ€”
*1 The variable check is from 0 to 24 MHz when the external check is used.  
287  
 
MSM80C154S/83C154S  
ยก Semiconductor  
(2) External program memory read cycle  
tLHLL  
ALE  
tAVLL  
tLLPL  
tPLPH  
tLLIV  
tPLIV  
PSEN  
tPXAV  
tPXIZ  
tLLAX tAZPL  
tPXIX  
INSTR  
IN  
PORT0  
PORT2  
A0 to A7  
A0 to A7  
tAVIV  
A8 to A15  
A8 to A15  
A8 to A15  
288  
 
ยก Semiconductor  
MSM80C154S/83C154S  
(3) External data memory access AC characteristics  
VCC=2.2 to 6.0V, VSS=0V, Ta=โ€“40ยฐC to +85ยฐC  
PORT 0, ALE, and PSEN connected with 100pF load, other connected with 80pF load  
*1  
Variable clock from  
1 to 24 MHz  
Parameter  
Symbol  
Unit  
Min.  
41.7  
Max.  
1000  
โ€”
XTAL1, XTAL2 Oscillator Cycle  
ALE Signal Width  
tCLCL  
tLHLL  
ns  
ns  
2tCLCL-40  
Address Setup Time  
tAVLL  
tLLAX  
1tCLCL-15  
1tCLCL-35  
โ€”
โ€”
ns  
ns  
(to ALE Falling Edge)  
Address Hold Time  
(from ALE Falling Edge)  
RD Signal Width  
tRLRL  
6tCLCL-100  
6tCLCL-100  
โ€”
โ€”
ns  
ns  
WR Signal Width  
tWLWH  
RAM Data Read Time  
(from RD Signal Falling Edge)  
RAM Data Read Hold Time  
(from RD Signal Rising Edge)  
Data Bus Floating Time  
(from RD Signal Rising Edge)  
RAM Data Read Time  
(from ALE Signal Falling Edge)  
RAM Data Read Time  
(from Address Output)  
RD/WR Output Time from ALE  
Falling Edge  
tRLDV  
tRHDX  
tRHDZ  
tLLDV  
tAVDV  
tLLWL  
tAVWL  
โ€”
0
5tCLCL-105  
โ€”
ns  
ns  
ns  
ns  
ns  
ns  
ns  
โ€”
โ€”
โ€”
2tCLCL-70  
8tCLCL-100  
9tCLCL-105  
3tCLCL+40  
โ€”
3tCLCL-40  
*2  
3tCLCL-100  
RD/WR Output Time from Address  
Output  
4tCLCL-70  
WR Output Time from Data Output  
Time from Data to WR Rising Edge  
Data Hold Time  
tQVWX  
tQVWH  
1tCLCL-40  
โ€”
โ€”
ns  
ns  
7tCLCL-105  
tWHQX  
tRLAZ  
2tCLCL-50  
0
โ€”
โ€”
ns  
ns  
ns  
(from WR Rising Edge)  
Time from to Address Float RD  
Output  
Time from RD/WR Rising Edge to  
ALE Rising Edge  
1tCLCL+40  
tWHLH  
1tCLCL-30  
*2  
1tCLCL+100  
*1 The variable check is from 0 to 24 MHz when the external check is used.  
*2 For 2.2ยฃV <4 V  
CC  
289  
 
MSM80C154S/83C154S  
ยก Semiconductor  
(4) External data memory read cycle  
tWHLH  
tLHLL  
ALE  
PSEN  
tLLDV  
tLLWL  
tRLRH  
RD  
tRHDZ  
t
AVLL tLLAX  
tRLDV  
tRHDX  
tAZRL  
A0toA7  
RrorDPL  
INSTR  
IN  
A0toA7  
PCL  
A0toA7  
PCL  
DATA IN  
PORT 0  
PORT 2  
tAVWL  
tAVDV  
PCH  
A8 to A15 PCH  
P2.0 to P2.7 DATA or A8 to A15 DPH  
A8 to A15 PCH  
(5) External data memory write cycle  
tWHLH  
tLHLL  
ALE  
PSEN  
tLLWL  
tWLWH  
WR  
tLLAX  
tQVWH  
tAVLL  
tWHQX  
tQVWX  
A0toA7  
RrorDPL  
INSTR  
IN  
A0 to A7  
PCL  
A0 to A7  
PCL  
PORT 0  
PORT 2  
DATA (ACC)  
tAVWL  
A8 to A15  
PCH  
A8 to A15 PCH  
P2.0 to P2.7 DATA or A8 to A15 DPH  
A8 to A15 PCH  
290  
 
ยก Semiconductor  
MSM80C154S/83C154S  
(6) Serial port (I/O Extension Mode) AC characteristics  
(VCC=2.2 to 6.0V, VSS=0V, Ta=โ€“40ยฐC to +85ยฐC)  
Parameter  
Symbol  
tXLXL  
Min.  
12tCLCL  
10tCLCL-133  
2tCLCL-75  
0
Max.  
Unit  
ns  
Serial Port Clock Cycle Time  
โ€”
Output Data Setup to Clock Rising Edge  
Output Data Hold After Clock Rising Edge  
Input Data Hold After Clock Rising Edge  
Clock Rising Edge to Input Data Valid  
tQVXH  
โ€”
โ€”
ns  
tXHQX  
ns  
tXHDX  
โ€”
ns  
tXHDV  
โ€”
10tCLCL-133  
ns  
291  
 
MACHINE  
CYCLE  
ALE  
tXLXL  
SHIFT  
CLOCK  
tQVXH  
tXHQX  
OUTPUT  
DATA  
tXHDX  
tXHDV  
INPUT  
DATA  
VALID  
VALID  
VALID  
VALID  
VALID  
VALID  
VALID  
VALID  
 
ยก Semiconductor  
MSM80C154S/83C154S  
(7) AC Characteristics Measuring Conditions  
1.Input/output signal  
VOH  
VOH  
VIH  
VIL  
VIH  
VIL  
TEST POINT  
VOL  
VOL  
*
The input signals in AC test mode are either V  
where logic "1" corresponds to a CPU output signal waveform measuring point in excess of  
(logic "1") or V (logic "0") input signals  
OH OL  
V
IH  
, and logic "0" to a point below V .  
IL  
2.Floating  
Floating  
VOH  
VOH  
VIH  
VIL  
VIH  
VIL  
VOL  
VOL  
*
The port 0 floating interval is measured from the time the port 0 pin voltage drops below V  
IH  
after sinking to GND at 2.4 mA when switching to floating status from a "1" output, and from  
thetimetheport0pinvoltageexceedsV afterconnectingtoa400 mAsourcewhenswitching  
IL  
to floating status from a "0" output.  
(8) XTAL1 external clock input waveform conditions  
Parameter  
External Clock Freq.  
Symbol  
1/tCLCL  
tCHCx  
Min.  
0
Max.  
24  
โ€”
โ€”
5
Unit  
MHz  
ns  
Clock Pulse width 1  
Clock Pulse width 2  
Rise Time  
15  
15  
โ€”
โ€”
tCLCX  
ns  
tCLCH  
ns  
Fall Time  
tCHCL  
5
ns  
External Clock Drive Waveform  
0.7 VCC  
0.2 VCC - 0.1  
EXTERNAL  
OSCILLATOR  
SIGNAL  
tCHCL  
tCLCH  
tCHCX  
tCLCX  
tCLCL  
293  
 
MSM80C154S/83C154S  
ยก Semiconductor  
Timing Diagram  
Basic timing  
294  
 

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